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发表于 2014-8-7 12:20:07
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显示全部楼层
請問你用的是什麼版本?
v1.0.5:
- void HardwareSerial::flush()
- {
- // UDR is kept full while the buffer is not empty, so TXC triggers when EMPTY && SENT
- while (transmitting && ! (*_ucsra & _BV(TXC0)));
- transmitting = false;
- }
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v1.5.6, v1.5.7:
- void HardwareSerial::flush()
- {
- // If we have never written a byte, no need to flush. This special
- // case is needed since there is no way to force the TXC (transmit
- // complete) bit to 1 during initialization
- if (!_written)
- return;
- while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) {
- if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0))
- // Interrupts are globally disabled, but the DR empty
- // interrupt should be enabled, so poll the DR empty flag to
- // prevent deadlock
- if (bit_is_set(*_ucsra, UDRE0))
- _tx_udr_empty_irq();
- }
- // If we get here, nothing is queued anymore (DRIE is disabled) and
- // the hardware finished tranmission (TXC is set).
- }
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